by Bob Zeidman
Hardware Description Languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize, and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design. This course teaches how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of Verilog language is explained in detail. By the end of the course, you will be able to design and simulate real hardware using Verilog. Course includes: Study guide, final exam, textbook: Verilog Designer's Library (Prentice Hall, 1999) and 1 CD-ROM, 8 CEUs and Certificate of Educational Achievement upon successful completion.
About the Author
Bob Zeidman is the president of Zeidman Consulting, a hardware and software contract development firm in Silicon Valley, California. He has designed ASICs, FPGAs, and PC boards for RISC-based parallel processor systems, laser printers, network switches and routers, and other real time systems. His clients have included Apple Computer, Cisco Systems, Ricoh Systems, and Texas Instruments. He has written several technical papers on hardware and software design methods, and has taught courses at engineering conferences throughout the country. He holds a Masterís degree from Stanford University and two Bachelorís degrees from Cornell University.